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Verilog_VCD 1.06

Module to Parse VCD (Value-Change-Dump) files

Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further analysis can be performed on the simulation data. The entire VCD file can be stored in a Python data structure and manipulated using standard hash and array operations.

More details in the module file : .

Originally written in Perl by Gene Sullivan ( . Translated into Python by Sameer Gauria ( . Patches submitted by Scott Chin, Sylvain Guilley, Bogdan Tabacaru.

File Type Py Version Uploaded on Size
Verilog_VCD-1.06.tar.gz (md5) Source 2015-07-14 5KB
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