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Verilog_VCD 1.05

Module to Parse VCD (Value-Change-Dump) files

Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further analysis can be performed on the simulation data. The entire VCD file can be stored in a Python data structure and manipulated using standard hash and array operations. This module is also a good helper for parsing fsdb files, since you can run fsd2vcd (part of the novas installation) to convert them to the vcd format and then use this module.

More details in the module file : Verilog_VCD.py .

Originally written in Perl by Gene Sullivan (gsullivan@cpan.org) . Translated into Python by Sameer Gauria (sgauria+python@gmail.com) .

 
File Type Py Version Uploaded on Size
Verilog_VCD-1.05.tar.gz (md5) Source 2014-02-28 5KB
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